The size, complexity, and speed of integrated circuits are increasing every year. At the same time, the reduction of size and weight is an extremely important goal, especially in applications such as aerospace, aviation, lap top computers, etc. And in the area of packaging, density translates directly into speed. Accordingly, the current trend is to house and interconnect multiple integrated circuits in the smallest area possible, often in a type of package referred to as a multi-chip module.
One type of multi-chip module utilizes solder bumps to attach integrated circuit die to a module substrate. Solder bumps are placed on the pads of the integrated circuit, the module, or both. The integrated circuit is then mated to the module substrate. A thermal cycle melts the solder and bonds the pad areas together. Generally, the module substrate has an interconnect network to route the integrated circuit's inputs and outputs to the rest of the system.
The solder bump technique has many advantages over other multi-chip module methods. However, the conventional solder bump approach does not address all packaging requirements. For example, since the solder bump connections are generally made between the under side of the integrated circuit die and the substrate, accurate placement is an issue. Also, it is difficult to test the individual integrated circuits for failures, once the integrated circuits are attached to the module. Even if individual defective integrated circuits are found, it is difficult to swap out defective integrated circuits for good ones.
Another aspect of multi-chip modules incorporating densely packed high power integrated circuits is that efficient heat dissipation is required. As integrated circuits are placed closer together, the power dissipation problem becomes aggravated. In the conventional solder bump attachment technique, the only contact the integrated circuits have with the module substrate is through the solder bumps. Yet, heat dissipation through the solder bump connections is not the best solution to the problem. For multi-chip modules with minimal heat dissipation requirements, thermal bumps can be added at the cost of active area or heat can be dissipated into the ambient via the back plane of the integrated circuit. However, for multi-chip modules with greater thermal dissipation requirements, complex attachments such as thermal conduction modules incorporating heat sinking or forced air are used, which increases the module complexity and cost.
Another recent approach to the size reduction goal is wafer scale integration in which many or all the integrated circuits necessary for a particular application are fabricated and interconnected on a single wafer. The problem with this approach is that numerous redundant integrated circuits must be designed into the wafer in order to accommodate failures. When the wafer is tested, bad die are disconnected and good die are connected into the circuit. Although this approach alleviates the need to remove bad die from a module and has better planarity, this is a very expensive solution, both in excess material cost and in excess size.
Accordingly, a solution to the size reduction goal for multi-chip integrated circuit packages is needed, which allows for easy placement of the integrated circuit die into the module, easy swapping of bad die for good die, and easy heat dissipation solutions, as well as optimum size reduction, and optimum module planarity.